Your Path to a Semiconductor Career

Design synthesizable RTL for ASICs and SoCs. Work on microarchitecture and block-level implementation in Verilog/SystemVerilog.

Build and execute UVM testbenches for complex digital blocks. Coverage-driven verification with assertion-based checking.

Own the floorplan to GDSII flow for ASIC blocks. Timing closure, power optimization, and signoff sign-off expertise.

Perform static timing analysis across corners. Identify and fix setup/hold violations, manage multicycle paths and false paths.

Design-for-test insertion: scan chains, BIST, JTAG boundary scan, ATPG patterns, and test coverage optimization.

DRC/LVS clean signoff using Calibre and IC Validator. Waive or fix violations for foundry-ready GDSII submission.

IR drop, electromigration (EM) analysis and fixing, power planning optimization, and dynamic power simulation.

FPGA-based SoC prototyping for pre-silicon validation. Work with Palladium/Zebu emulation platforms for system-level testing.