// ANALOG LAYOUT TRACK

Analog Layout Design

From device physics to DRC/LVS-clean silicon. Master Cadence Virtuoso Layout XL with real analog circuit layouts and matching techniques — in 30 weeks.

// LAYOUT DESIGN FLOW

Analog Layout Design Flow

Device Physics

→

CMOS Fabrication

→

Virtuoso XL

→

DRC / LVS

→

Matching & AMS

→

PEX / RCX

→

Signoff ✓

// CURRICULUM ROADMAP

8 Phases · 30 Weeks

Phase 01 · Weeks 1–4

Device Physics & CMOS Fundamentals

Foundations of R, L, C, KCL/KVL, characteristics of Diodes, BJT, and MOS devices. Advanced CMOS concepts for layout engineers.

R, L & C Basics KCL / KVL Diode Characteristics BJT MOS Transistor CMOS Concepts

Phase 02 · Weeks 5–7

IC Fabrication & Technology Nodes

IC and CMOS fabrication steps, device cross-sections, sub-micron and deep sub-micron technology nodes.

IC Fabrication Steps CMOS Fabrication Device Cross-sections Sub-micron Tech Deep Sub-micron Technology Nodes

Phase 03 · Weeks 8–11

Cadence Virtuoso Layout XL — Tool Mastery

Linux environment for layout, Virtuoso Layout XL tool flow, technology layers, library/cell creation, P-Cells, DRC/ERC/LVS, and parasitic extraction.

Linux for Layout Virtuoso Layout XL Technology Layers Library & Cell Views P-Cell DRC / ERC / LVS RCX / PEX Post-Layout Sim

Phase 04 · Weeks 12–15

Standard Cell Layout

Full-custom and schematic-driven layouts for standard digital cells: Inverter, NAND/NOR, AND/OR, Latch and Flip-Flop.

Inverter (NOT) NAND / NOR AND / OR Latch Flip-Flop Schematic-driven Layout Full-Custom Layout

Phase 05 · Weeks 16–18

Matching Concepts & Layout Issues

Device mismatch sources, interdigitated and common-centroid matching, EM/IR drop, latch-up, crosstalk, shielding, antenna effects, and ESD basics.

Mismatches Interdigitated Matching Common-Centroid EM / IR Drop Latch-Up Crosstalk & Shielding Antenna ESD Concepts

Phase 06 · Weeks 19–23

Analog & Mixed-Signal Layouts

Hands-on layout practice on real analog circuits: Single Stage Amplifier, Current Mirror, and Two Stage Op-Amp.

Single Stage Amplifier Current Mirror Two Stage Op-Amp AMS Layout Techniques

Phase 07 · Weeks 24–25

Layout Dependent Effects (LDE)

Deep sub-micron second-order effects that impact layout: STI, LOD, WPE, short/narrow channel effects, substrate bias, and layout visualizations.

STI (Shallow Trench Isolation) LOD (Length of Diffusion) WPE (Well Proximity Effect) Short Channel Effects Narrow Channel Effects Substrate-Bias Effect Layout Visualizations

Phase 08 · Weeks 26–30

Advanced Layout Techniques

Advanced layout options, floorplan, power planning, guard-rings, full DRC/LVS signoff, and interview preparation.

Floorplan & Power Planning Placement & Routing Guard-Rings DRC / LVS Signoff Parasitic Extraction Interview Prep

// TOOLS & SKILLS

What You'll Master

🎛️

Layout Skills

▸ Full-custom and schematic-driven layout

▸ Interdigitated and common-centroid matching

▸ Analog circuit layouts: amplifiers, mirrors, op-amps

▸ Guard-ring design and power planning

▸ Layout-dependent effects (STI, LOD, WPE)

✅

Verification & Signoff

▸ DRC (Design Rule Check) and ERC

▸ LVS (Layout vs Schematic) debug and closure

▸ Parasitic extraction (RCX / PEX)

▸ Post-layout simulation and correlation

▸ Antenna and ESD rule checking

⚙️

EDA Tools Covered

▸ Cadence Virtuoso Layout XL

▸ Cadence Assura / PVS (DRC & LVS)

▸ Cadence Quantus / RCX (Parasitic Extraction)

💡

RECOMMENDED ADD-ON

Scripting & Automation Track

Linux · Shell · TCL · Python for VLSI — pair it with Analog Layout and get a bundle discount.

// ENROLL NOW

Ready to Start Your Analog Layout Journey?

Next batch starts soon. Limited seats. Book your free demo session today.