Go deep into how modern processors and accelerators actually work. Master RISC-V ISA from encoding to pipeline micro-architecture, and GPU design from SIMT execution to memory hierarchy — the skills that define architecture engineers at NVIDIA, ARM, Intel, and Qualcomm.
// ARCHITECTURE JOURNEY
From ISA to Micro-Architecture
ISA & Encoding
→
Pipeline Design
→
Memory Hierarchy
→
GPU Math & Memory
→
Graphics Pipeline
→
GPU Capstone ✓
// TWO PILLARS
What You'll Master
🔲
// PILLAR 1
RISC-V Architecture
Understand the open RISC-V ISA from base integer instructions to standard extensions. Explore instruction encoding formats, privilege levels, pipeline design, hazard handling, branch prediction, custom ISA extensions, and RISC-V Vector (RVV) programming.
RV32I / RV64IM / F / D / C / A Ext5-Stage PipelineHazard HandlingPrivilege LevelsCustom ISARVV (Vector Extension)
🎮
// PILLAR 2
GPU Architecture & Graphics Pipeline
Go from GPU math fundamentals to a real open-source GPU. Master the complete 3D graphics pipeline — coordinate transforms, rasterization, depth testing, and fragment shading — then map it onto Vortex, an open RISC-V-based GPU you can build and run.
Complete mastery of the RISC-V ISA — every instruction format, encoding, and standard extension. Run and debug real assembly on Spike.
RV32I / RV64I base ISAInstruction formats: R / I / S / B / U / JM / F / D / A / C / Zicsr extensionsABI & calling conventions🧪 Hands-On Lab
02
Module 02 · Weeks 5–8 · Pipeline Design
5-Stage Pipeline, Hazards & Branch Prediction
Design and simulate a complete 5-stage RISC-V pipeline. Understand structural, data, and control hazards, forwarding paths, and branch prediction — the foundation of all processor design.
IF → ID → EX → MEM → WB pipelinePipeline registers & data path designStructural / Data / Control hazardsForwarding paths & load-use stallBTB / BHT (1-bit & 2-bit) / Tournament / RASIntroduction to Out-of-Order concepts🧪 Hands-On Lab
Master CPU cache design — direct-mapped and set-associative caches, LRU/PLRU replacement, write policies, and MESI cache coherence. A critical module missing from most courses.
Understand the RISC-V privilege model — the foundation of OS and firmware. Master CSRs, trap handling, CLINT/PLIC, and Sv39 virtual memory with a hands-on bare-metal lab.
Extend RISC-V with domain-specific custom instructions and learn vectorized programming using the RISC-V Vector Extension (RVV) — the two most powerful RISC-V customization features used in industry.
Custom opcode space (custom-0 to custom-3)GCC toolchain extension for custom instructionsRISC-V Vector Extension (RVV) — vsetvl, vle, vse, vadd, vmulVectorized programming with RVV intrinsicsScalar vs vector performance comparison🧪 Hands-On Lab
G1
Module G1 · GPU Track · Math Foundation
Intro to Math for the GPU
Build the mathematical foundation every GPU engineer needs. Coordinate spaces, vectors, matrices, and the complete MVP pipeline — all walked step-by-step with real numbers, ending with a working mat4×vec4 transform unit.
Why bandwidth dominates graphics. A complete study of framebuffer, Z-buffer, stencil, texture memory, and tiled rendering — with direct callbacks to GPU caches vs MESI and GPU MMU vs Sv39 from the RISC-V modules.
Why bandwidth dominates graphicsFramebuffer, Z-buffer (depth) & stencilTexture memory — mipmaps, filtering, texture cacheTiled rendering & compressionDRAM/bandwidth · GPU caches vs MESI · GPU MMU vs Sv39🧪 Hands-On Lab
G3
Module G3 · GPU Track · Graphics Pipeline
The Graphics Pipeline
Fixed-function vs programmable stages — walked end to end with real numbers. From vertex processing and primitive assembly through rasterization via edge functions, perspective-correct interpolation, fragment shading, and the output-merger.
Fixed-function vs programmable stagesVertex processing, primitive assembly & clippingBack-face cullingRasterization via edge functions (walked with real numbers)Perspective-correct interpolation & fragment shadingROP / output-merger🧪 Hands-On Lab
G4
Module G4 · GPU Track · Open-Source GPU
Open-Source GPU Architecture (Vortex)
Maps everything in G1–G3 onto a real open GPU — Vortex, a RISC-V-based GPU. Just-enough SIMT, Vortex micro-architecture, its 3D graphics pipeline (rasterizer, texture unit, output-merger), warp scheduling, and building/running Vortex.
Vortex — open-source RISC-V-based GPUJust-enough SIMT — lanes, warps, masksVortex micro-architecture walkthrough3D graphics pipeline in Vortex — rasterizer, texture, output-mergerWarp scheduling in VortexBuilding & running Vortex from source🧪 Hands-On Lab
G5
Module G5 · GPU Track · Capstone
Capstone: a Graphics GPU Block
Integrates G1–G3 into a mini pipeline: transform → rasterize → depth-test → write. Students work across Modelling / RTL / Verification roles with milestones and sign-off. The fragment processor renders a full scene — two overlapping triangles with correct depth.
Deep dives into AXI4, AXI-Lite, AXI-Stream, AMBA CHI, ACE, APB, and AHB protocols. Understand how SoC interconnects work at the signal and transaction level.
AXI4AMBA CHIAPB / AHBAXI-Stream
🚀
// UPCOMING
High-Speed I/O Protocols
PCIe Gen 4/5 architecture, DDR4/DDR5/LPDDR5 memory subsystems, and NVMe. From protocol layers to SoC integration — for engineers working on high-bandwidth system design.
PCIe Gen5DDR5 / LPDDR5NVMeHBM2e
💻
// UPCOMING
CPU & System Architectures
ARM v8/v9 architecture, out-of-order execution, superscalar pipelines, SoC interconnect fabrics, and AI/ML accelerator architectures — for engineers targeting CPU and DSA design roles.
ARM v8/v9Out-of-OrderSuperscalarAI Accelerators
// TOOLS & TECHNOLOGIES
Tools You'll Work With
🔲
RISC-V GNU GCC
Toolchain
📡
Spike ISS
Golden Reference
🎮
Vortex GPU
Open-Source RISC-V GPU
🐍
Python 3
Simulation & Modelling
🔭
Gem5 Simulator
Arch Simulation
🐧
GDB / Linux
Debug Environment
📁
Git / CMake
Build & Version
// WHY THIS COURSE
Skills That Make You an Architecture Engineer
🔲
RISC-V Is the Future of Open Silicon
Open, extensible, and royalty-free — RISC-V is adopted by Google, NVIDIA, Western Digital, and India's national semiconductor initiative. Deep ISA and micro-architecture knowledge is in high demand.
🎮
GPU Architecture Is the Hottest Skill in Tech
AI/ML acceleration has made GPU micro-architecture knowledge one of the most sought-after skills globally. Understanding SM design, warp scheduling, and memory hierarchy commands top-tier compensation.
🏗️
Architecture Exploration
Architecture engineers evaluate design trade-offs — area vs performance vs power — before committing to RTL. This analytical mindset is what separates architects from RTL designers.
📈
Performance Analysis Skills
Learning to use roofline models, IPC analysis, and warp occupancy profiling gives you the tools to quantify and communicate architecture trade-offs — a critical skill in any chip design review.
🌍
Roles That Don't Exist Yet
AI accelerator architecture, domain-specific ISA design, and heterogeneous SoC architecture are growth areas creating entirely new job categories. This track puts you ahead of that curve.
📋
Industry-Ready Portfolio
Graduate with a RISC-V pipeline analysis project, a GPU performance model, and an architecture trade-off report — exactly the kind of work that impresses architecture hiring managers.
// ENROLL NOW
Ready to Think Like an Architecture Engineer?
Next batch starts soon. Limited seats available. Book your free demo session today.
// Architecture Curriculum
RISC-V Architecture · GPU Micro-Architecture
9 Modules · Labs in Every Module · RISC-V + GPU Capstone Project
MODULE 1
RISC-V Base ISA & Standard Extensions
Weeks 1–4 · Complete ISA mastery — assembly labs on Spike & QEMU
M1
RISC-V ISA Deep Dive — RV32I/RV64I + All Extensions
Weeks 1–4 · Encoding · semantics · ABI · standard extensions
▶
RV32I / RV64I — base integer ISA, all 47 instructionsInstruction formats: R / I / S / B / U / J encodingM extension — MUL, MULH, DIV, REMF/D — IEEE 754 single & double precision FPA extension — LR/SC & AMO atomicsC extension — 16-bit compressed instructionsZicsr — CSRRW, CSRRS, CSRRC, CSRRWIABI & calling conventions (RISC-V psABI)