Weeks 10–15 · Cadence Innovus · Die sizing → macro placement → power grid design
3.1
Floorplan Initialization & Die Sizing
Core area, aspect ratio, utilization, IO ring
►
Die area & core area calculationAspect ratio selectionCore utilization target (70–80%)IO pad placement & ring planningCorner cells & filler cellsRectilinear floorplansBlockages (hard, soft, partial)Halos around macrosChip-level vs block-level floorplanningFloorplan quality metrics (HPWL, congestion)
3.2
Macro Placement & Pin Assignment
Memory/IP placement, channel routing, data flow orientation
►
Macro placement objectives (data flow, timing, area)Memory compiler orientation & abutmentAnalog/mixed-signal IP placementChannel routing between macrosMacro-to-macro spacing rulesPin assignment — primary input/output locationsBus grouping & bit orderingFeedthrough planningPartition-level interface planningLab: Full floorplan with 4 memory macros — timing-aware
3.3
Power Planning & Power Grid Design
VDD/VSS rings, straps, mesh, power rails — IR drop budgeting
►
Power domain definition (VDD, VSS, VDDIO)Power ring sizing & placementPower strap width & pitch calculationPower mesh topology (H-tree, grid, star)Standard cell rail (VDD/VSS rows)Follow-pin connectionsIR drop budget (static & dynamic)Electromigration (EM) current density limitsPower domain isolation cellsUPF-driven multi-voltage floorplanDecap cell insertion strategyLab: Power grid design with Cadence Voltus IR analysis
Global routing (GR) — resource allocationTrack assignmentDetail routing — via optimizationNDR routing rules for critical netsClock net routing (shielding, NDR)Signal integrity — crosstalk noise analysisAntenna rule violations & fixesRouting DRC fixing (spacing, short, open)Via doubling / via ladderingMetal fill insertionFiller cell insertionLab: Full routing run — DRC-clean with congestion analysis
5.2
Static Timing Analysis (STA) — Full Signoff
Cadence Tempus — setup/hold, MCMM, ECO flow
►
STA fundamentals — timing paths (data, clock)Setup time & hold time equationsSlack calculation (WNS / TNS / NVP)Clock domain crossing timing (async paths)CPPR — Common Path Pessimism RemovalParasitic extraction — SPEF, RC cornersPVT corners (process: SS/FF/TT, voltage, temp)MMMC analysis — all corners simultaneouslySignoff ECO — fixing violations at layout levelreport_timing — path analysis & debugreport_constraint — exceptions validationFalse path & multicycle path validationLab: Full STA signoff with Cadence Tempus — MCMM closure
5.3
Power Analysis & IR Drop / EM Signoff
Cadence Voltus — static & dynamic IR, electromigration
►
Static power analysis — leakage currentDynamic power analysis — switching activityVCD / SAIF activity annotationStatic IR drop analysisDynamic IR drop analysisIR drop hotspot identification & fixingElectromigration (EM) — average & RMS currentEM violation fixing — metal width upsizingPower grid strengtheningDecap insertion for dynamic IRPower budget reportingLab: IR drop & EM analysis with Cadence Voltus
5.4
Signal Integrity & Crosstalk Analysis
Noise-on-delay, glitch analysis, SI-aware routing
►
Capacitive coupling & crosstalk mechanismsNoise-on-delay (pessimistic / optimistic)Glitch noise analysis (SI-threshold)Victim / aggressor net identificationSI-aware CTS fixingShielding critical nets (VDD/VSS guards)Wire spacing increase for SI fixBuffer insertion for noise immunitySI timing signoff with SPEF parasitics
PHASE 6
Physical Verification & GDSII Tapeout Signoff
Weeks 27–32 · Cadence Calibre · DRC → LVS → ERC → antenna → metal fill → GDSII
Electrical rule checks, antenna violations, foundry fill requirements
►
ERC — floating gate detectionERC — power/ground short detectionAntenna effect mechanism (gate oxide damage)Antenna ratio calculation (metal/via area)Antenna violation fixing (jumper via, antenna diode)Metal density requirements per layerAutomated metal fill insertion (dummy fill)Metal fill impact on timing (parasitic)Via maximization for reliabilityCMP (Chemical Mechanical Planarization) density rules
6.4
GDSII Tapeout & Signoff Checklist
Final tapeout flow — GDSII streaming, layer map, sign-off checklist
►
GDSII stream out (Virtuoso / Innovus)Layer map file preparationTop-level GDSII merge (chip + IP + IO)GDSII validation (Calibre DRC final run)LVS final run on merged GDSIISTA final signoff — all PVT corners cleanIR drop final signoff — all domains cleanEM final signoffTapeout checklist (100-point verification)Foundry PDK submission packageLab: End-to-end mini chip tapeout — GDSII to foundry format
6.5
ECO (Engineering Change Order) Flow
Post-mask ECO, functional ECO, metal-only ECO
►
Functional ECO — logic change implementationTiming ECO — setup/hold fix at layoutMetal-only ECO — no new diffusion masksSpare cell methodologyECO cell placement constraintsIncremental routing after ECOECO verification (LVS / DRC re-check)Formal verification of ECO correctnessPost-ECO STA sign-off